| Summary: | 碩士 === 國立成功大學 === 電機工程研究所 === 83 === Current technologies for manufacturing VLSI and PCB circuits
are so complex that the traditional testing method cannot deal
well with these circuits. This problem can be effectively
solved by using digital boundary scan testing (i.e., IEEE Std.
1149.1) if only digital circuits are concerned. However analog
or mixed- mode circuit testing is still a difficult problem. In
this thesis we develop a new mixed--mode boundary scan
architecture. The digital part of this architecture complies
with IEEE Std. 1149.1. For the analog part, we propose a new
analog boundary scan cell, present the required test control
circuits, and define 4 analog test instructions. The Hspice and
VHDL simulators are used to verify the analog boundary scan
cell and the control circuits, respectively. Compared with
previous analog boundary scan design, our architecture has the
following advantages. (1) Signals at various test points can be
sampled simultaneously, (2) test stimuli can be injected to
various test points simultaneously, (3) test stimuli loading
and test response outputting can be done simultaneously, and
(4) both DC and AC testing are allowed. In addition to the
hardware design, we also develop a system to automatically
generate digital and/or analog boundary scan circuitry for a
circuit described in VHDL. To make the system easy to use, a
user--friendly graphic interface has been implemented on the
SUN workstation under the Openwin environment. Using this
system, one can easily add boundary scan circuits to any
designed applications.
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