Date-Based Controller Synthesis----Engineering Verification (I)
碩士 === 國立成功大學 === 航空太空工程學系 === 83 === A numerical process based technique for control system synthesis is proposed. The method is applicable when the system is open-loop stable. The major features of this method are two folds. First, a corr...
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1995
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| Online Access: | http://ndltd.ncl.edu.tw/handle/92662376843626301415 |
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ndltd-TW-083NCKU02950532015-10-13T12:53:36Z http://ndltd.ncl.edu.tw/handle/92662376843626301415 Date-Based Controller Synthesis----Engineering Verification (I) 基於取樣數據之控制器設計----工程驗証之壹 L-H Chein 簡榮皇 碩士 國立成功大學 航空太空工程學系 83 A numerical process based technique for control system synthesis is proposed. The method is applicable when the system is open-loop stable. The major features of this method are two folds. First, a correlation equation is established between the open-loop system response and the desired closed-loop system model parameters. As a result, it is possible to synthesize the controllers from a batch of plant test data without the explicit knowledge of a parameterize plant model. Second. the workability of the synthesized controller may be verified in due process, even at the absence of the open-loop system model. The major purpose of this reserch is to verify this theory through experimental means. Jenq-Tzong H.Chan 陳正宗 1995 學位論文 ; thesis 49 zh-TW |
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Others
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碩士 === 國立成功大學 === 航空太空工程學系 === 83 === A numerical process based technique for control system
synthesis is proposed. The method is applicable when the system
is open-loop stable. The major features of this method are two
folds. First, a correlation equation is established between the
open-loop system response and the desired closed-loop system
model parameters. As a result, it is possible to synthesize the
controllers from a batch of plant test data without the
explicit knowledge of a parameterize plant model. Second. the
workability of the synthesized controller may be verified in
due process, even at the absence of the open-loop system model.
The major purpose of this reserch is to verify this theory
through experimental means.
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| author2 |
Jenq-Tzong H.Chan |
| author_facet |
Jenq-Tzong H.Chan L-H Chein 簡榮皇 |
| author |
L-H Chein 簡榮皇 |
| spellingShingle |
L-H Chein 簡榮皇 Date-Based Controller Synthesis----Engineering Verification (I) |
| author_sort |
L-H Chein |
| title |
Date-Based Controller Synthesis----Engineering Verification (I) |
| title_short |
Date-Based Controller Synthesis----Engineering Verification (I) |
| title_full |
Date-Based Controller Synthesis----Engineering Verification (I) |
| title_fullStr |
Date-Based Controller Synthesis----Engineering Verification (I) |
| title_full_unstemmed |
Date-Based Controller Synthesis----Engineering Verification (I) |
| title_sort |
date-based controller synthesis----engineering verification (i) |
| publishDate |
1995 |
| url |
http://ndltd.ncl.edu.tw/handle/92662376843626301415 |
| work_keys_str_mv |
AT lhchein datebasedcontrollersynthesisengineeringverificationi AT jiǎnrónghuáng datebasedcontrollersynthesisengineeringverificationi AT lhchein jīyúqǔyàngshùjùzhīkòngzhìqìshèjìgōngchéngyànzhèngzhīyī AT jiǎnrónghuáng jīyúqǔyàngshùjùzhīkòngzhìqìshèjìgōngchéngyànzhèngzhīyī |
| _version_ |
1716868251317698560 |