An Implementation of Two-Level Cache Controller

• Main Authors: Huang,Biing-Huang, 黃炳煌
• Other Authors: Chang, Si En
• Format: Others
• Language: zh-TW
• Published: 1995
• Online Access: http://ndltd.ncl.edu.tw/handle/98820523625021840667

碩士 === 中原大學 === 資訊工程研究所 === 83 === Cache memory is utilized to bridge the speed gap between CPU and main memory. The advance of VLSI technology makes many techniques to explore instruction level parallelism are applied in many high performance CPUs. However, the improvement of main memory is not as fast as that of CPU. The gap between main memory and CPU is getting bigger. When the difference in cycle times between the main memory and the CPU is increasing, there is a need to bridge that larger gap in several smaller steps such as two-level cache. The objective of this thesis is to implement a two-level cache controller based on MIPS R2000/ R3000 instruction set CPU. The two-level cache controller is able to control a two-level cache hierarchy in which the first level is split instruction and data caches, and the second level is a unified cache. A behavior model of MIPS R2000/R3000 CPU has been constructed as a testbed to verify all cache models established in the thesis. A behavior model and a gate- level model of a single level cache controller are first designed and verified as a foundation to be expanded. The gate- level model of the single level cache controller is extended to a two-level cache controller. All models are described by Verilog hardware description language. The basic cells utilized in the gate-level models are from CCL 0.8um cell library. Based on the timing provided by the cell library, the timing of the gate-level model has been verified. The two-level cache controller has been routed in a chip with 7.7mm * 7.7mm die size and 160 pads by Cadence cell ensemble auto-routing method.