Fast 16-bit x 16-bit Multiplier by Using Residue Number System
碩士 === 淡江大學 === 資訊工程研究所 === 82 === It always needs much multiplication and addition in digital signal precessing systems, and the speed of a multiplier is the key point of whole system's performance; therefore, it is necessary to...
Main Authors: | Shyh- Chang Jang, 張世昌 |
---|---|
Other Authors: | Jen- Shiun Chiang |
Format: | Others |
Language: | zh-TW |
Published: |
1994
|
Online Access: | http://ndltd.ncl.edu.tw/handle/30121027120191572721 |
Similar Items
Similar Items
-
A Fast 16-bit/16-bit Divider by Using Residue Number System
by: Jer-Yu Tzou, et al.
Published: (1995) -
The Design of 16x16 bit Booth Multiplier with Asynchronous Pipeline Technique
by: Meng-Hsuan Ho, et al.
Published: (2011) -
A 16-Bit LSI Digital Multiplier
by: Masumoto, Rodney Tak
Published: (1978) -
The Design of a 16-bit Asynchronous Multiplier
by: Wu Chun Lung, et al.
Published: (2005) -
Power-efficient design of 16-bit mixed-operand multipliers
by: Pornpromlikit, Sataporn, 1979-
Published: (2005)