| Summary: | 碩士 === 淡江大學 === 資訊工程研究所 === 82 === It always needs much multiplication and addition in digital
signal precessing systems, and the speed of a multiplier is the
key point of whole system's performance; therefore, it is
necessary to fulfill a high speed multiplier. In this thesis,
we will apply the theory of residue number systems (RNS) to
implement a 16-bit x 16-bit high speed multi- plier. All the
arithmetic operations in RNS are accomplished by each modulus,
and the moduli in the RNS are independent of each other.
Therefore, we do not need to worry about the propaga- tions
among the moduli and hence the arithmetic is very fast. In
addition, the "multiplication" is transformed into
"addition" by the special operation of Galois field. So the
system is equipped with properties of high speed. A VLSI
experimental chip is fabricated. The fabrication technology
is CMOS 0.8um DPDM process which is provided by Chip
Implementation Center (CIC) of the National Science Council
(NSC) of the Republic of China. We design the chip, and finish
all the procedures of simulation, lay-out, and verification. On
chip testing is also applied to verify the multiplier.
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