| Summary: | 博士 === 國立臺灣大學 === 電機工程研究所 === 82 === DSP synthesis for IC design has become a major component in the
rapidly expanding field of Application Specific Integrated
Circuit design. To synthesis ASICs for DSP, a number of
synthesis tasks, behavioral synthesis and physical synthesizer,
are used to convert an algorithm description of circuit
behavior into the final layout. The major problem on DSP
synthesis system is how to employed DSP theorems and design
principles, such as the critical throughput rate and the
iterative execution nature of DSP algorithms, a hardware
description easy for design documentation and familiar to DSP
designers, and a friendly user interface and the hardware trade-
off algorithm for DSP designer who is not familiar to VLSI
design. In this dissertation, we study the problems in DSP
synthesis based on the requirement of area cost and speed
performance, including the hardware description language and
compilation, the graphic user interface, the module set and
clock cycle selection, and the optimal throughput rate
scheduling of DSP algorithms, and a design automation syste for
the DSP chip design. The contributions of this dissertation are
described as follows: 1. The graphic user interface in chapter
3 provides a friendly block-diagram editor with the debugging
and verifying capabilities. 2. A hardware description language
which is to generate a data flow graph for DSP synthesis with
less operators and evaluation times. 3. The module and clock
cycle selection algorithm helps user begin their DSP design
with a reasonable initial module set. 4. A novel pipelining and
unfolding scheduling is developed to get an optimal throughput
rate design.
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