The Behavior of Bilateral Latch-Up Triggering in VLSI CMOS Protection Circuits

• Main Authors: Heng-Sheng Huang, 黃恆盛
• Other Authors: C. Y. Chang
• Format: Others
• Language: en_US
• Published: 1993
• Online Access: http://ndltd.ncl.edu.tw/handle/29247230366336779482

博士 === 國立交通大學 === 電子研究所 === 82 === The results of serial studies on the behavior of bilateral latch-up in CMOS protection circuits are presented. Latch-up and ESD problems are two major factors that degrade VLSI pro- duct reliability. A new latch-up phenomenon showing symmetrical diac-similar I-V characteristics has been discovered recently. Electrical measurements show that a diac-similar parasitic semi- conductor-controlled-rectifier (SCR) device can exist between two adjacent ESD protection circuits or output buffers. The SCR consists of two parasitic PNPN paths and can easily induce a localized SCR latch-up between two adjacent input or output ter- minals. This is a new bilateral latch-up path between two ad- jacent input and output pins. A new latch-up failure mode due to this diac-similar structure, which creates a bilateral path during the temperature humidity bias (THB) testing discussed. The failure mode can be observed and verified by cross section techniques or latch-up triggering test experimentation. Some suggestions regarding how to improve this diac-similar latch-up degradation are proposed. Advanced analyses and modeling are also presented in this paper. The modified lumped element model explains this diac-similar latch- up phenomenon. Bilateral latch up self-triggering resulting from series resistance or series inductance on Vdd or Vss is discussed. Optimizing the layout and design of output buffers to improve product performance and re- liability is also recommended. The studies on the behavior of bilateral latch up in CMOS protection circuits are more important since low power applications are becoming the future trends.