The design and implementation of a rendering accelerator for computer graphics

• Main Authors: Chan-Liang Chen, 陳建良
• Other Authors: Chein-Wei Jen
• Format: Others
• Language: en_US
• Published: 1994
• Online Access: http://ndltd.ncl.edu.tw/handle/11091408373186179999

碩士 === 國立交通大學 === 電子研究所 === 82 === A Raster Engine( RE ) is designed and implemented to improve the performance of computer graphics and image composition. The RE hardware can release more than 50% CPU loads. Furthermore, if the approximated Phong method which is new proposed is 89% CPU operations are reduced. As the features of this design, the techniques including modified digitral differentail analyser (modified DDA), 2-level pipeline, and constant execution time for calculating cos^n\theta, are proposed in RE. Three operation modes: Gouraud, Phong and composition are incorporated in RE. The simulation results show that the system can operate up to 50MHz. As the result, the pixel update rate is 6M/sec for Gouraud shading and composition, and 3M/sec for Phong shading. The gate count of this chip is about 22K, and the die size is 7684.5um * 7444.8um. This chip is designed and implemented by using ITRI/CCL 0.8um CMOS cell library, and it will be fabricated by SPDM technology in TSMC.