Parameters programmable fast sequential decoder design using high speed sorter
碩士 === 國立交通大學 === 電子研究所 === 82 === This paper presents a new sequential decoding algorithm, its VLSI architecture and circuit layout for long constraint length convolutional code design in digital communications. This new algorithm is based...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
1994
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| Online Access: | http://ndltd.ncl.edu.tw/handle/01334473292086231398 |