Boron Penetration in Different Gate Microstructures of P+ Poly- Gate PMOS Capacitors

• Main Authors: Kuei-Chi Juan, 阮桂棋
• Other Authors: Chun-Yen Chang
• Format: Others
• Language: en_US
• Published: 1994
• Online Access: http://ndltd.ncl.edu.tw/handle/21247120342814951808

碩士 === 國立交通大學 === 電子研究所 === 82 === P型閘極P型金氧半元件中之硼擴散至氧化層效應,可以用多晶矽閘極予以 抑制.除此之外,在多晶矽閘極結構中的界面,可以進一步提高硼穿透所需 克服的位能障.應用多晶矽於閘極的上層,顯示出比較小的臨界電壓平移 值,較小的電子受陷速率,比較平滑的閘極表面形態和較大的崩潰電荷.在 多晶矽沉積後加上熱回火,硼穿透效應和氧化層品質可以同時達到改善的 目的. The effect of boron diffusion through the thin oxide in p+- gate PMOS devices can be suppressed by using an amorphous-Si gate. In addition, the interface in amorphous-Si gate structure can further increase the barrier for boron penetration. The use of amorphous-Si as the upper-layer gate exhibits a smaller flatband voltage shift, a less electron trapping rate, a more smooth gate surface morphology and a larger charge-to- breakdown. By thermal annealing after amorphous-Si deposition, an improvement both in boron penetration and gate oxide quality can be achieved simultaneously.