A VLSI Design of Error-Correction Decoder for Digital VTR in D-3 Format

• Main Authors: Jian-Dai Pan, 潘建岱
• Other Authors: Che-Ho Wei
• Format: Others
• Language: en_US
• Published: 1994
• Online Access: http://ndltd.ncl.edu.tw/handle/01005490429652585332

碩士 === 國立交通大學 === 電子研究所 === 82 === The error-correcting-codes(ECC) system contributes largely to the quality improvement in the new generation of video products. A high speed ECC system is implemented following the D-3 format for the television digital recording. In the inner code, a modified four-stage pipelined algorithm is proposed to decode the (95,87) shortened RS code. In the outer code, we adopted an extended two-stage pipelined algorithm to decode the (136,128) shortened RS code. Both algorithms can evidently shorten the system clock comparing to the traditional structures. Using the proposed algorithms, two decoder chips for the inner and outer code are implemented. The area of the inner code decoder chip is 4.9mm by 4.9mm, with about 90000 transistors. The area of the outer code decoder chip is 4.9mm by 4mm, with about 65000 transistors. One external reset control signal and one single phase clock are used for both chips. The simulated data rate by IRSIM is over 200 Mbps and is over the requirement of D-3 format (63.3Mbps).