| Summary: | 碩士 === 國立交通大學 === 資訊科學學系 === 82 === In this thesis, we present a new method based on graph theory
to solve the problem of allocation of multiport memories. Based
on the target architecture of two-phase clocking scheme, to
enhance the ports utilization of multiport memory, we make the
same port be written on the first phase and read on the second
one. By such way, we can save many cost of internal connections
(or control signals), and eliminate some unnecessary "pure data
transfer" operations. Under such principle, we overcome the
problem of allocation of multiport memories by three steps: (1)
Partitioning of variables: it is mainly according to the
conditions of variables being used. We solve it by graph
theory. It is not only partitioning the variables according to
the conditions of being used, but also producing fewer
registers. (2) Connecting of ports : it connects ports with the
registerd produced in step (1). Here , we adapt Left-Edge
algorithm. (3) Interconnections minimization : minimize the
cost of interconnections between ports and functional units.
Here, we adapt linear programming method from MAP. Experimental
results show that the method we presented is very effective,
and get a promising result.
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