| Summary: | 碩士 === 國立交通大學 === 資訊科學學系 === 82 === The major source of parallelism in ordinary programs is do
loops. When loop iterations of parallelized loops are executed
on a shared memory multiprocessors system, the cross-iteration
data dependences need to be enforced by synchronization
instructions to ensure the correct execution. Existing data
synchronization schemes are either too restrictive to be
practical, or too inefficient due to large run-time overhead.
In this thesis, we propose a hardware mechanism to eliminate
the necessity of synchronization instructions which is required
by former schemes to be embedded into loops, ensuring the data
dependences. Also, the usage of critical section is not needed
at all due to skillful design of our hardware architecture.
Furthermore, according to the analysis, the run-time overheads
of our architecture is small to be acceptable. So we may
conclude that to execute loops over multiple processors, our
method is believed to be good compared with former researches.
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