Algorithms for Performance-Directed Layout Compaction

• Main Authors: Lih-Yang Wang, 王立洋
• Other Authors: Yen-Tai Lai, Bin-Da Liu
• Format: Others
• Language: en_US
• Published: 1994
• Online Access: http://ndltd.ncl.edu.tw/handle/79608449889572581501

博士 === 國立成功大學 === 電機工程研究所 === 82 === As the requirement of high performance circuit grows ra- pidly, a compaction algorithm is not only expected to reduce the layout area, but also to improve the circuit performance . Conventional compactors first compact the layout size, and then minimize the total weighted wire length, hence the to- tal wire RC effect. In this dissertation, a new performance- directed layout compaction methodology is proposed. This approach first mi- nimizes the interconnection RC effects along timing critical paths, and then compacts the layout. The compaction problem is solved by 1-D compaction approach, where the problem is formulated into two successive linear programming problems. Two efficient algorithms, one is based on the the reduction of constraints and the other is a graph- based Simplex algo- rithm, are developed to solve the two linear programming problems. Experimental results show that both algorithms are very efficient.