| Summary: | 碩士 === 中原大學 === 電子工程學系 === 82 === In RF circuit design, the stable frequency source is usually
generated by crystal oscillator. THe crystal oscillator is a
stable frequency source, but it can generate a limited number
frequencies, and the frequencies can be modified in small
region only. Most wireless equipments need many stable
frequency sources. For instance, a SSB transceiver require
280,000 frequencies of signals with 100Hz frequency seperation
between 2 -30MHz region. The Phase-Locked Loop (PLL) techniques
can be applied to generate those stable and precise
frequencies. In this thesis, we study the frequency synthesizer
and reaize a hardware whose frequency band are in the region of
300-400MHz, and the frequency seperation is 10KHz. The total
number of frequencies is 10,000. The frequency synthesizer
consists of a quicker PLL and a circuit divider. The ICs are
used in the fabrication, then the complication of the frequency
synthesizer circuit design is greatly redused. The measurements
of the parameters of the frequency synthesizer are compared
with the theoretical values, we also discuss the differences
and indicate the way how to improve the performance.
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