Synthesis of multilevel multioutput NAND gate logic network and its CAD design using permissible cubes and PCRM graph
碩士 === 中原大學 === 電子工程學系 === 82 === The subject of two-level logic synthesis is well developed and well understood. In contrast, multilevel logic synthesis is less studied, more difficult, and relatively new. Nevertheless, multilevel logic s...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
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1994
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| Online Access: | http://ndltd.ncl.edu.tw/handle/41329223087882599806 |