Design and Analysis of Self-Dual Multipliers

• Main Authors: Jia-Pei Shen, 沈嘉珮
• Other Authors: Cheng-Wen Wu
• Format: Others
• Language: zh-TW
• Published: 1993
• Online Access: http://ndltd.ncl.edu.tw/handle/86823411056932041464

碩士 === 國立清華大學 === 電機工程研究所 === 81 === We present the theoretical foundations and universal ap- proach for design for testability and design for test compa- ctibility on path delay faults. Simple tests and modified c- ube distance are introduced, which are the basis of our der- ivation. Our method has the characteristic that to change the testability requirement in different regions of circuits can be done easily. The obstacle of design for testability in multilevel ci- rcuits is to properly control conceptualized cubes of equi- valent normal form(ENF). Our analysis can greatly reduce the required memory and computational complexity to evaluate or choose the control points and the types of control gate. We prove that primality and code-disjointness are suffi- cient conditions for hazard-free robust testability. Accord- ingly, we develop a simple procedure which combines design- -for- testability and synthesis-for-testability concepts to fulfill the design of completely hazard-free robust testable circuits. The upper bound of required extra inputs of this method is 「 ㏒ ξ.ilperp., where ξ is the maximal number of primary inputs on which a primary output depends. The proce- dure is feasible and suitable to multiple-output functions, which compensates for the weakness of existing methods. Combining this strategy with the developed general desi- gn for testability method, we can get a good design quickly but still possess the flexibility of design. Our method is complete.