FPGA Technology Mapping Using Cut_and_encode Method

• Main Authors: Yang, Hann Der, 楊漢德
• Other Authors: Hwang, Ting Ting
• Format: Others
• Language: en_US
• Published: 1993
• Online Access: http://ndltd.ncl.edu.tw/handle/74151086815875466372

碩士 === 國立清華大學 === 資訊科學學系 === 81 === Field Programmable Gate Array(FPGA) is a new technology that provides users the programmability in the field. The short rapid prototyping and low manufacturing cost have made FPGA an important technology for VLSI ASIC design. There are mainly two types of FPGA architecture : one is based on table lookup (e. g., Xilinx), the other is based on multiplexers (e.g., Actel). In this thesis, we focus on the Table Look_Up(TLU) architecture. A basic cell in the TLU architecture is called a configurable logic block (CLB). It can realize any function of up to k inputs. In XC3000 series, k is 5. The interconnections between the logic blocks consists of metal segments joined by program-controlled pass transistors. The logic functions and the interconnections are determined by the configuration program data stored in the internal static memory cells. Technology mapping is a process of transforming technology independent Boolean network into technology-based circuit. For TLU-based FPGAs, a technology mapper decomposes the Boolean network into a set of subnetworks such that each subnetwork is implemented using a CLB. Since a traditional technology mapper needs an explicit library definition, it is not feasible to enumerate all the functions that a RAM cell can perform. For example, in the Xilinx 3000 series, each CLB has 5 inputs, so we must have 2^(2^5) explicit library entries if we use the traditional technology mapper. Thus, the traditional technology mapper is not suitable for FPGA mapping. We propose a new technology mapper in this thesis. Two techniques are used. One is based on Roth_Karp decomposition and the other Boolean substitution. Both techniques are developed on the Binary Decision Diagrams.