A Performance Driven Placement Algorithm For FPGAs

• Main Authors: Lin, Whe Dar, 林慧達
• Other Authors: Hwang，Ting Ting
• Format: Others
• Language: zh-TW
• Published: 1993
• Online Access: http://ndltd.ncl.edu.tw/handle/64593975287687098014

碩士 === 國立清華大學 === 資訊科學學系 === 81 === In this paper, we propose a performance driven placement method for FPGAs. The proposed system first assigns the levels of the network using as-soon-as-possible method and finds the relative locations by a bipartite weighted matching algorithm. It then searches for the network shape to fit into the given FPGA architecture. Lastly, a bipartite-weighted-matching is performed again to assign cells into the new shape. Our method is able to produce a shorter critical path delay compared to other placement methods. Experimental results on two sets of benchmarks that the proposed system is indeed very effective in minimizing the real delay after routing.