| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 81 === Though advanced technology allows to put large computation
power on a signal processor chip, the accessing ability of
a signal processor may become another limitation on
its performance. This is the motivation to study efficient
address generation method. In this thesis, we develop a
useful and efficient synthesis tool, SAG (Synthesizer
for Address Generation), for automatic construction
of the address generator. The only thing which user should
do is to write a behavior description for the desired
address sequence. With the behavior description as
input, the synthesizer SAG will construct the address
generation circuit in the form of Verilog net-list as
Output. This net-list consists of counters and
combinational logics and represented in the form of modules.
Test results show that the output net-lists satisfy the
specifications and occupy very small chip area. Thus this
SAG synthesizer provide an efficient way to design
address generation for performance improvement of signal
processing chips.
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