Architectural Design of a Programmable Viterbi Decoder

• Main Authors: Ming-Chang Tsai, 蔡明昌
• Other Authors: Kuei-Ann Wen
• Format: Others
• Language: en_US
• Published: 1993
• Online Access: http://ndltd.ncl.edu.tw/handle/89436649013582259356

碩士 === 國立交通大學 === 電子研究所 === 81 === The Viterbi algorithm (VA) used in decoding convolutional code is widely used in modern communications. For the widely use of Viterbi decoder, we proposed a programmable Viterbi decoder (VD) in this thesis. The performance of VD is better when the constraint length K ( K = m+1 , m is register length ) is larger. However, the complexity increase exponentially with K. Via software simulation , we specify the design parameters for the programmable VD to decode the ( 2, 1, m ) convolutional codes with m = 2, 3, 4, and 5 and choose the truncation length to be 20. The VD can be programmed by given any generator polynomials with constraint length less than 6. The architecture is the node-serial. The best state decoding (BSD) method can be easily constructed with node-serial structure to save a lot of chip area for path memory. The survivor path memory is constructed by register-exchange method with only simple control circuit needed. By 1.2 micro meter CMOS technology, the operating clock rate can be up to 35 MHz and the final chip size is 4.9 mm x 6.8 mm.