| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 81 === In this thesis, we proposed and implemented some procedures to
do the data path synthesis in Field Programmable Gate Arrays
(FPGAs). This thesis involves the following issues : (1). How
to build and select the cell library. (2). The input format.
(3). To select the intermediate representation. (4). The
algorithm of cell placement. (5). Select the routing algorithm
and routability analysis. (6). Algorithm of pin assignment.
(7). Transfer the result to the Xilinx's format. Due to the bit
sliced nature of the data path,the two dimensional placing and
routing problem of symmetrical architecture is reduced to a one
dimensional one. We studied and implemented several placement
algorithms and compared results. The router is using a modified
version of a previously published method called Coarse graph
expansion (CGE).The current system is deigned for Xilinx XC3000
FPGA chips. In the future, we hope to upgrade the result to
XC4000 series and extend our algorithms to two dimensional
placement and routing problems.
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