| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 81 === The partial scan design methodology has been recognized as a
cost-efficient technique to improve the testability of
sequential circuits. In this thesis, a flip-flop's value
oriented partial scan approach is proposed. The main idea
pursued here is to derive a flip-flop selection strategy just
from the useful and easily accessed information in the test
generation (TG) process. Parameters of UC, SR, TC, and RF are
created and updated based on the value of flip-flop. In the end
of TG, they are integrated to guide the decision making on flip-
flop selection priority. Neither enormous arithmetic
computation nor complicated processing is needed in our
approach. Also experimental results show that higher fault
coverage can be achieved by selecting less flip-flops and
inputing less test patterns than those in ETD for most
benchmaek circuits.
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