VLSI Design of Viterbi Decoder for PR-IV Magnetic Recording Channels
碩士 === 國立交通大學 === 電子研究所 === 81 === In this thesis, a 2-state, radix-16, six-level soft-decision Viteri decoder over 300M bps is designed and simulated using 0.8-um double-metal CMOS. Application of partial-response(PR) signaling and maximum...
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| Format: | Others |
| Language: | en_US |
| Online Access: | http://ndltd.ncl.edu.tw/handle/75163221478508363230 |
| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 81 === In this thesis, a 2-state, radix-16, six-level soft-decision
Viteri decoder over 300M bps is designed and simulated using
0.8-um double-metal CMOS. Application of partial-response(PR)
signaling and maximum-likelihood sequence detection(MLSD) to
digital magnetic recording had been derived and applied to
increase the storage densities and reliability. To perform
partial-response MLSD at the high data rates, a novel
implementation of the Viterbi detector using carry-save
arithmetic is proposed and allows each word-level and bit-level
operation to be pipelined. A cascadable module is designed to
speed-up the decoding rate to meet the requirement.
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