Shift Register Array Architectures for High-Speed Data Sorting
碩士 === 國立交通大學 === 電子研究所 === 81 === In this thesis, an architecture style named shift register array (SRA) for high speed data sorting is represented. In addition, two architectures and an ASIC based on this architecture sty...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Online Access: | http://ndltd.ncl.edu.tw/handle/3e2j22 |