Shift Register Array Architectures for High-Speed Data Sorting

• Main Authors: Jer-Min Tsai, 蔡哲民
• Other Authors: Chen-Yi Lee
• Format: Others
• Language: en_US
• Online Access: http://ndltd.ncl.edu.tw/handle/3e2j22

碩士 === 國立交通大學 === 電子研究所 === 81 === In this thesis, an architecture style named shift register array (SRA) for high speed data sorting is represented. In addition, two architectures and an ASIC based on this architecture style are represented,too. In this architecture style, input sample is simultaneously compared with all sorted samples, where the former can be routed to any location, while the latter can only be routed to their neighborhoods. With this architecture, we achieve the minimum latency delay for sorting each input sample. The two architectures in this thesis show that the latency can be reduced to WL cycles (Here WL is the wordlength of input samples) in M-array architecture and 1 cycle in ODI architecture. The M-array algorithm is first transformed to a bar-chart like style which is then implemented on the SRA architecture, and finally an M-array ASIC is implemented. The test results show that the SRA architecture can perform the function of median filtering. The ODI sorter based on insertion-sort provides a fast and less area hardware solution for sorting. Evaluation shows that it is very suitable to be implemented as a high- speed general-purpose sorter.