Design and Analysis of Special Integrated Power Devices in CMOS Technology

• Main Authors: Gwo-Ming Chen, 陳國明
• Other Authors: Chung-Yu Wu
• Format: Others
• Language: en_US
• Published: 1993
• Online Access: http://ndltd.ncl.edu.tw/handle/27484005253354116070

碩士 === 國立交通大學 === 電子研究所 === 81 === In this thesis, two fully CMOS process compatible special power devices called the GTO and the CMCT are proposed. First, the operation of each special device is introduced. The main operational principle of the device is based on that of the parasitic SCR formed by the parasitic pnp and npn transistors in bulk CMOS. From the SPICE simulation results with their corresponding lumped equivalent circuits, the design techniques to implement these special power devices in CMOS are developed. The layout pattern to realize these devices is of the interdigitated style. This kind of layout shape has been commonly used in planar power bipolar transistors. The method to integrate the special power devices into a chip with other normal CMOS devices are also discussed. The characteristics of the special power devices with different layout spacings are investigated by SPICE simulation. These results can be applied to the design of these devices. The devices have been fabricated by 0.8um CMOS p-substrate double-poly double-metal CMOS technology with different device spacings which could have different device performance. The I-V curves and the switching waveforms of the special power devices with different layout spacings are also measured and analyzed. Both simulation results and measured results show a good consistence which substantiates the function of the special devices.