Performance Evaluation of a Data-Driven Hybrid Computer Architecture

• Main Authors: Kuang-Hweia Chi, 紀光輝
• Other Authors: Chien-Chao Tseng
• Format: Others
• Language: zh-TW
• Published: 1993
• Online Access: http://ndltd.ncl.edu.tw/handle/29608433458295169638

碩士 === 國立交通大學 === 資訊工程研究所 === 81 === The combination of dataflow and von Neumann execution models is a recent trend in designing high speed processors. In this thesis, an analytical model of a novel data-driven hybrid computer architecture is presented and a simulation of the arch- itecture is also conducted to verify the correctness of the ana- lytical model. Similar to the Monsoon architecture developed at MIT, the underline of the presented architecture is a data-driven pipelined processor. However, it differs from the Monsoon archi- tecture in the sense that only enabled instructions can enter the pipeline. Nevertheless, as noted in the thesis, there could be two instructions which issue memory accesses simultaneously in the pipe of the proposed architecture: one instruction assem- bling its operands and another writing its results. Therefore, the memory system must be able to support two to four simultan- eous memory accesses in one pipeline cycle. Clearly, the memory system would be the bottleneck of the architecture if it is not designed properly. Hence, the analytical model is constructed based on various configurations of the memory system: various degrees of memory interleaving and different numbers of write buffers. The evaluation results show that the proposed architec- ture can easily achieve high performance with small degree of interleaving as well as number of write buffers.