A Performance Driven Technology Mapping for Lookup Table-Based Field Programmable Gate Arrays

碩士 === 國立成功大學 === 電機工程研究所 === 81 === In this thesis, we present a graph-based technology mapping algorithm that minimize the delay of combinational circuits implemented with lookup table-based Field Programmable Gate Arrays(FPGA) architectu...

Full description

Bibliographic Details
Main Authors: Yao-Xing Hwang, 黃耀興
Other Authors: Yen-Tai Lai
Format: Others
Language:zh-TW
Published: 1993
Online Access:http://ndltd.ncl.edu.tw/handle/05920234571460349653
id ndltd-TW-081NCKU0442102
record_format oai_dc
spelling ndltd-TW-081NCKU04421022016-07-20T04:11:35Z http://ndltd.ncl.edu.tw/handle/05920234571460349653 A Performance Driven Technology Mapping for Lookup Table-Based Field Programmable Gate Arrays 效能導向現場可規劃閘陣列之映對 Yao-Xing Hwang 黃耀興 碩士 國立成功大學 電機工程研究所 81 In this thesis, we present a graph-based technology mapping algorithm that minimize the delay of combinational circuits implemented with lookup table-based Field Programmable Gate Arrays(FPGA) architecture. There are mainly two types of FPGA architecture: one is based on lookup table(LUT), and the other is based on multiplexers. In this thesis, we concentrate on the former type of FPGA architecture. An FPGA chip contains many Configurable Logic Blocks(CLB) each of which can realize any logic function of k inputs. Technology mapping for FPGA is a process of transforming a Multi-level logic gate boolean network into a CLB-based circuit. It is a collection of logic blocks connected together. Traditional techniques for technology mapping use a library of basic cells. However, these technology mapping techniques are not suitable for lookup table- based FPGA architectures.  There are two main objectives in technology mapping for FPGA: one is to reduce the number of CLBs(reducing area), and the other is to reduce the number of level of CLB(reducing delay). One important issue is the tradeoff between reducing the number of CLBs and reducing the number of level. This thesis focuses on technology mapping for the delay optimization of FPGAs. We assume the delay of all FPGA blocks is the same. In this thesis, the critical path delay is measured by the number of level of CLBs on the path. We present heuristic methods for the reducing levels. First we perform minimization using Mis-II system. Next we transform the input boolean network into a Gate_network. Eventually, we transform the Gate_network into CLB_network. We compare our method to several existing approaches. And we confirm the effectiveness of this approach by the experimental results. Yen-Tai Lai 賴源泰 1993 學位論文 ; thesis 67 zh-TW
collection NDLTD
language zh-TW
format Others
sources NDLTD
description 碩士 === 國立成功大學 === 電機工程研究所 === 81 === In this thesis, we present a graph-based technology mapping algorithm that minimize the delay of combinational circuits implemented with lookup table-based Field Programmable Gate Arrays(FPGA) architecture. There are mainly two types of FPGA architecture: one is based on lookup table(LUT), and the other is based on multiplexers. In this thesis, we concentrate on the former type of FPGA architecture. An FPGA chip contains many Configurable Logic Blocks(CLB) each of which can realize any logic function of k inputs. Technology mapping for FPGA is a process of transforming a Multi-level logic gate boolean network into a CLB-based circuit. It is a collection of logic blocks connected together. Traditional techniques for technology mapping use a library of basic cells. However, these technology mapping techniques are not suitable for lookup table- based FPGA architectures.  There are two main objectives in technology mapping for FPGA: one is to reduce the number of CLBs(reducing area), and the other is to reduce the number of level of CLB(reducing delay). One important issue is the tradeoff between reducing the number of CLBs and reducing the number of level. This thesis focuses on technology mapping for the delay optimization of FPGAs. We assume the delay of all FPGA blocks is the same. In this thesis, the critical path delay is measured by the number of level of CLBs on the path. We present heuristic methods for the reducing levels. First we perform minimization using Mis-II system. Next we transform the input boolean network into a Gate_network. Eventually, we transform the Gate_network into CLB_network. We compare our method to several existing approaches. And we confirm the effectiveness of this approach by the experimental results.
author2 Yen-Tai Lai
author_facet Yen-Tai Lai
Yao-Xing Hwang
黃耀興
author Yao-Xing Hwang
黃耀興
spellingShingle Yao-Xing Hwang
黃耀興
A Performance Driven Technology Mapping for Lookup Table-Based Field Programmable Gate Arrays
author_sort Yao-Xing Hwang
title A Performance Driven Technology Mapping for Lookup Table-Based Field Programmable Gate Arrays
title_short A Performance Driven Technology Mapping for Lookup Table-Based Field Programmable Gate Arrays
title_full A Performance Driven Technology Mapping for Lookup Table-Based Field Programmable Gate Arrays
title_fullStr A Performance Driven Technology Mapping for Lookup Table-Based Field Programmable Gate Arrays
title_full_unstemmed A Performance Driven Technology Mapping for Lookup Table-Based Field Programmable Gate Arrays
title_sort performance driven technology mapping for lookup table-based field programmable gate arrays
publishDate 1993
url http://ndltd.ncl.edu.tw/handle/05920234571460349653
work_keys_str_mv AT yaoxinghwang aperformancedriventechnologymappingforlookuptablebasedfieldprogrammablegatearrays
AT huángyàoxìng aperformancedriventechnologymappingforlookuptablebasedfieldprogrammablegatearrays
AT yaoxinghwang xiàonéngdǎoxiàngxiànchǎngkěguīhuàzházhènlièzhīyìngduì
AT huángyàoxìng xiàonéngdǎoxiàngxiànchǎngkěguīhuàzházhènlièzhīyìngduì
AT yaoxinghwang performancedriventechnologymappingforlookuptablebasedfieldprogrammablegatearrays
AT huángyàoxìng performancedriventechnologymappingforlookuptablebasedfieldprogrammablegatearrays
_version_ 1718354217457942528