| Summary: | 碩士 === 國立成功大學 === 電機工程研究所 === 81 === In this thesis, we present a graph-based technology mapping
algorithm that minimize the delay of combinational circuits
implemented with lookup table-based Field Programmable Gate
Arrays(FPGA) architecture. There are mainly two types of FPGA
architecture: one is based on lookup table(LUT), and the other
is based on multiplexers. In this thesis, we concentrate on the
former type of FPGA architecture. An FPGA chip contains many
Configurable Logic Blocks(CLB) each of which can realize any
logic function of k inputs. Technology mapping for FPGA is a
process of transforming a Multi-level logic gate boolean
network into a CLB-based circuit. It is a collection of logic
blocks connected together. Traditional techniques for
technology mapping use a library of basic cells. However, these
technology mapping techniques are not suitable for lookup table-
based FPGA architectures. There are two main objectives in
technology mapping for FPGA: one is to reduce the number of
CLBs(reducing area), and the other is to reduce the number of
level of CLB(reducing delay). One important issue is the
tradeoff between reducing the number of CLBs and reducing the
number of level. This thesis focuses on technology mapping for
the delay optimization of FPGAs. We assume the delay of all
FPGA blocks is the same. In this thesis, the critical path
delay is measured by the number of level of CLBs on the path.
We present heuristic methods for the reducing levels. First we
perform minimization using Mis-II system. Next we transform the
input boolean network into a Gate_network. Eventually, we
transform the Gate_network into CLB_network. We compare our
method to several existing approaches. And we confirm the
effectiveness of this approach by the experimental results.
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