| Summary: | 碩士 === 國立成功大學 === 電機工程研究所 === 81 === Along with the advancing of VLSI technology, there is a need
for capturing behavioral specification of complex systems.
In this paper, Zodiak multi-level hardware specification
language and its Rule-Based Zodiak-to-VHDL Translator are
presented. Zodiak is constructed on an underlying model of
hierarchical/ concurrent state transition diagrams, while
retaining the ability of hardware structural design
capturing and design attribute specification. It provides
efficient and flexible modeling of behavior hierarchy/
concurrency and synchronous/ asynchronous synchronization
schemes. Communication mechanism such as global signal,
message queue, and semaphore are supported in Zodiak
which largely extend the capability of modeling abstract
inter-behavior communication. Furthermore, a new visual/
graphic representation formalism permitting concise and
comprehensive graphic behavioral-plus-structural design
representation are constructed to lead the Zodiak to be not
only a multi-level textual specification language but also a
multi- level graphic specification language. An efficient
Rule-Based Zodiak-to-VHDL Translator implemented in Prolog on
Sun Sparc2 is constructed for the simulation purpose. The power
and usefulness of the Zodiak is demonstrated through
modeling of couples of real examples, which are well
translated by the Rule-Based Translator and are
successfully simulated by Synopsys VHDL simulation tools.
The sizes of the target VHDL representations are in average
3-4 times larger than the original Zodiak representations.
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