Mapping Nested Loop Algorithms into Grid-Connected Systolic Arrays without Data Collisions in the Data Links
碩士 === 國立中正大學 === 電機工程研究所 === 81 === Systolic arrays, which are made out of simple processing elements connected by data links,have made significient improvements in speeding up computation in comparision to conventional computers. Although...
Main Authors: | Chen, Cheng Font, 陳正豐 |
---|---|
Other Authors: | Lee, Pei Zong |
Format: | Others |
Language: | en_US |
Published: |
1993
|
Online Access: | http://ndltd.ncl.edu.tw/handle/93759738839315705071 |
Similar Items
-
Fault-tolerance approaches for 3-data flow systolic arrays
by: Boulos, Tarek Rizkallah
Published: (1991) -
Automatic Storage Optimization of Arrays Affine Loop Nests
by: Bhaskaracharya, Somashekaracharya G
Published: (2018) -
On design of systolic arrays
by: SUN, PEI-ZHEN, et al.
Published: (1987) -
Extracting data flow information for parallelizing FORTRAN nested loop kernels
by: Walker, Edward
Published: (1994) -
Systolic array mapping of sequential algorithm for VLSI architecture
by: MA, YI-ZHENG, et al.
Published: (1986)