A hierarchical multi-level test generator for VHDL-Based designs
碩士 === 國立成功大學 === 電機工程研究所 === 80 ===
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Online Access: | http://ndltd.ncl.edu.tw/handle/67749746494819425929 |
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ndltd-TW-080NCKU24420612016-02-17T04:16:59Z http://ndltd.ncl.edu.tw/handle/67749746494819425929 A hierarchical multi-level test generator for VHDL-Based designs 針對VHDL所發展之階式多層次測試訊號產生器 YOU, SHENG-QUAN 游勝全 碩士 國立成功大學 電機工程研究所 80 ZHOU, ZHE-MIN 周哲民 1992 學位論文 ; thesis 73 en_US |
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en_US |
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Others
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碩士 === 國立成功大學 === 電機工程研究所 === 80 ===
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author2 |
ZHOU, ZHE-MIN |
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ZHOU, ZHE-MIN YOU, SHENG-QUAN 游勝全 |
author |
YOU, SHENG-QUAN 游勝全 |
spellingShingle |
YOU, SHENG-QUAN 游勝全 A hierarchical multi-level test generator for VHDL-Based designs |
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YOU, SHENG-QUAN |
title |
A hierarchical multi-level test generator for VHDL-Based designs |
title_short |
A hierarchical multi-level test generator for VHDL-Based designs |
title_full |
A hierarchical multi-level test generator for VHDL-Based designs |
title_fullStr |
A hierarchical multi-level test generator for VHDL-Based designs |
title_full_unstemmed |
A hierarchical multi-level test generator for VHDL-Based designs |
title_sort |
hierarchical multi-level test generator for vhdl-based designs |
publishDate |
1992 |
url |
http://ndltd.ncl.edu.tw/handle/67749746494819425929 |
work_keys_str_mv |
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