A hierarchical multi-level test generator for VHDL-Based designs

A hierarchical multi-level test generator for VHDL-Based designs

碩士 === 國立成功大學 === 電機工程研究所 === 80 ===

Bibliographic Details
Main Authors:	YOU, SHENG-QUAN, 游勝全
Other Authors:	ZHOU, ZHE-MIN
Format:	Others
Language:	en_US
Published:	1992
Online Access:	http://ndltd.ncl.edu.tw/handle/67749746494819425929

Description
Summary:	碩士 === 國立成功大學 === 電機工程研究所 === 80 ===