On loop scheduling for homogeneous VLIW architecture

On loop scheduling for homogeneous VLIW architecture

碩士 === 逢甲大學 === 機械工程研究所 === 80 ===

Bibliographic Details
Main Authors: YU, JUN-YI, 于駿逸
Other Authors: YANG, RUI-ZHONG
Format: Others
Language:zh-TW
Published: 1992
Online Access:http://ndltd.ncl.edu.tw/handle/38823237380745837901
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spelling ndltd-TW-080FCU024890012016-02-17T04:17:04Z http://ndltd.ncl.edu.tw/handle/38823237380745837901 On loop scheduling for homogeneous VLIW architecture 齊次性極長指令電腦之迴路排程 YU, JUN-YI 于駿逸 碩士 逢甲大學 機械工程研究所 80 YANG, RUI-ZHONG 楊濬中 1992 學位論文 ; thesis 145 zh-TW
collection NDLTD
language zh-TW
format Others
sources NDLTD
description 碩士 === 逢甲大學 === 機械工程研究所 === 80 ===
author2 YANG, RUI-ZHONG
author_facet YANG, RUI-ZHONG
YU, JUN-YI
于駿逸
author YU, JUN-YI
于駿逸
spellingShingle YU, JUN-YI
于駿逸
On loop scheduling for homogeneous VLIW architecture
author_sort YU, JUN-YI
title On loop scheduling for homogeneous VLIW architecture
title_short On loop scheduling for homogeneous VLIW architecture
title_full On loop scheduling for homogeneous VLIW architecture
title_fullStr On loop scheduling for homogeneous VLIW architecture
title_full_unstemmed On loop scheduling for homogeneous VLIW architecture
title_sort on loop scheduling for homogeneous vliw architecture
publishDate 1992
url http://ndltd.ncl.edu.tw/handle/38823237380745837901
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AT yújùnyì onloopschedulingforhomogeneousvliwarchitecture
AT yujunyi qícìxìngjízhǎngzhǐlìngdiànnǎozhīhuílùpáichéng
AT yújùnyì qícìxìngjízhǎngzhǐlìngdiànnǎozhīhuílùpáichéng
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