Physical timing models of COMS logic gates and their applications in timing analysis and transistor sizing

博士 === 國立交通大學 === 電子工程研究所 === 78 ===

Bibliographic Details
Main Authors: HUANG,ZHEN-SHENG, 黃振昇
Other Authors: WU,CHONG-YU
Format: Others
Language:zh-TW
Published: 1990
Online Access:http://ndltd.ncl.edu.tw/handle/65244217379956567393