Physical timing models of COMS logic gates and their applications in timing analysis and transistor sizing

博士 === 國立交通大學 === 電子工程研究所 === 78 ===

Bibliographic Details
Main Authors:	HUANG,ZHEN-SHENG, 黃振昇
Other Authors:	WU,CHONG-YU
Format:	Others
Language:	zh-TW
Published:	1990
Online Access:	http://ndltd.ncl.edu.tw/handle/65244217379956567393

id	ndltd-TW-078NCTU2428002
record_format	oai_dc
spelling	ndltd-TW-078NCTU24280022015-10-13T15:21:05Z http://ndltd.ncl.edu.tw/handle/65244217379956567393 Physical timing models of COMS logic gates and their applications in timing analysis and transistor sizing 互補式金氧半場效電晶體邏輯閘之時序模式及自動化電晶體尺寸設計之電腦輔助設計程式 HUANG,ZHEN-SHENG 黃振昇博士國立交通大學電子工程研究所 78 WU,CHONG-YU 吳重雨 1990 學位論文 ; thesis 216 zh-TW
collection	NDLTD
language	zh-TW
format	Others
sources	NDLTD
description	博士 === 國立交通大學 === 電子工程研究所 === 78 ===
author2	WU,CHONG-YU
author_facet	WU,CHONG-YU HUANG,ZHEN-SHENG 黃振昇
author	HUANG,ZHEN-SHENG 黃振昇
spellingShingle	HUANG,ZHEN-SHENG 黃振昇 Physical timing models of COMS logic gates and their applications in timing analysis and transistor sizing
author_sort	HUANG,ZHEN-SHENG
title	Physical timing models of COMS logic gates and their applications in timing analysis and transistor sizing
title_short	Physical timing models of COMS logic gates and their applications in timing analysis and transistor sizing
title_full	Physical timing models of COMS logic gates and their applications in timing analysis and transistor sizing
title_fullStr	Physical timing models of COMS logic gates and their applications in timing analysis and transistor sizing
title_full_unstemmed	Physical timing models of COMS logic gates and their applications in timing analysis and transistor sizing
title_sort	physical timing models of coms logic gates and their applications in timing analysis and transistor sizing
publishDate	1990
url	http://ndltd.ncl.edu.tw/handle/65244217379956567393
work_keys_str_mv	AT huangzhensheng physicaltimingmodelsofcomslogicgatesandtheirapplicationsintiminganalysisandtransistorsizing AT huángzhènshēng physicaltimingmodelsofcomslogicgatesandtheirapplicationsintiminganalysisandtransistorsizing AT huangzhensheng hùbǔshìjīnyǎngbànchǎngxiàodiànjīngtǐluójízházhīshíxùmóshìjízìdònghuàdiànjīngtǐchǐcùnshèjìzhīdiànnǎofǔzhùshèjìchéngshì AT huángzhènshēng hùbǔshìjīnyǎngbànchǎngxiàodiànjīngtǐluójízházhīshíxùmóshìjízìdònghuàdiànjīngtǐchǐcùnshèjìzhīdiànnǎofǔzhùshèjìchéngshì
_version_	1717764271812640768

Physical timing models of COMS logic gates and their applications in timing analysis and transistor sizing

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