The state diagram verification and test response compression for sequential circuits

碩士 === 國立成功大學 === 電機工程研究所 === 78 ===

Bibliographic Details
Main Authors:	LIU,SHI-YUN, 劉世運
Other Authors:	WANG,JUN-FA
Format:	Others
Language:	zh-TW
Published:	1990
Online Access:	http://ndltd.ncl.edu.tw/handle/67369958929543874144

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spelling	ndltd-TW-078NCKU24420512015-10-13T15:21:03Z http://ndltd.ncl.edu.tw/handle/67369958929543874144 The state diagram verification and test response compression for sequential circuits 序向電路狀態圖驗證及其響應壓縮測試法 LIU,SHI-YUN 劉世運碩士國立成功大學電機工程研究所 78 WANG,JUN-FA LIU,BIN-DA 王駿發劉濱達 1990 學位論文 ; thesis 70 zh-TW
collection	NDLTD
language	zh-TW
format	Others
sources	NDLTD
description	碩士 === 國立成功大學 === 電機工程研究所 === 78 ===
author2	WANG,JUN-FA
author_facet	WANG,JUN-FA LIU,SHI-YUN 劉世運
author	LIU,SHI-YUN 劉世運
spellingShingle	LIU,SHI-YUN 劉世運 The state diagram verification and test response compression for sequential circuits
author_sort	LIU,SHI-YUN
title	The state diagram verification and test response compression for sequential circuits
title_short	The state diagram verification and test response compression for sequential circuits
title_full	The state diagram verification and test response compression for sequential circuits
title_fullStr	The state diagram verification and test response compression for sequential circuits
title_full_unstemmed	The state diagram verification and test response compression for sequential circuits
title_sort	state diagram verification and test response compression for sequential circuits
publishDate	1990
url	http://ndltd.ncl.edu.tw/handle/67369958929543874144
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The state diagram verification and test response compression for sequential circuits

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