A study of high speed CMOS floating point multiply/accumulate chip based on redundant binary representation

碩士 === 國立交通大學 === 電子研究所 === 77 ===

Bibliographic Details
Main Authors:	WU, JI-LI, 吳基立
Other Authors:	SHEN, WEN-REN
Format:	Others
Language:	zh-TW
Published:	1989
Online Access:	http://ndltd.ncl.edu.tw/handle/14874956461527063537

id	ndltd-TW-077NCTU2430054
record_format	oai_dc
spelling	ndltd-TW-077NCTU24300542016-07-29T04:13:11Z http://ndltd.ncl.edu.tw/handle/14874956461527063537 A study of high speed CMOS floating point multiply/accumulate chip based on redundant binary representation 高速互補式金氧半浮點乘加運算積體電路設計以多餘二位元表示之研究 WU, JI-LI 吳基立碩士國立交通大學電子研究所 77 SHEN, WEN-REN 沈文仁 1989 學位論文 ; thesis 111 zh-TW
collection	NDLTD
language	zh-TW
format	Others
sources	NDLTD
description	碩士 === 國立交通大學 === 電子研究所 === 77 ===
author2	SHEN, WEN-REN
author_facet	SHEN, WEN-REN WU, JI-LI 吳基立
author	WU, JI-LI 吳基立
spellingShingle	WU, JI-LI 吳基立 A study of high speed CMOS floating point multiply/accumulate chip based on redundant binary representation
author_sort	WU, JI-LI
title	A study of high speed CMOS floating point multiply/accumulate chip based on redundant binary representation
title_short	A study of high speed CMOS floating point multiply/accumulate chip based on redundant binary representation
title_full	A study of high speed CMOS floating point multiply/accumulate chip based on redundant binary representation
title_fullStr	A study of high speed CMOS floating point multiply/accumulate chip based on redundant binary representation
title_full_unstemmed	A study of high speed CMOS floating point multiply/accumulate chip based on redundant binary representation
title_sort	study of high speed cmos floating point multiply/accumulate chip based on redundant binary representation
publishDate	1989
url	http://ndltd.ncl.edu.tw/handle/14874956461527063537
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A study of high speed CMOS floating point multiply/accumulate chip based on redundant binary representation

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