A study of high speed CMOS floating point multiply/accumulate chip based on redundant binary representation

A study of high speed CMOS floating point multiply/accumulate chip based on redundant binary representation

碩士 === 國立交通大學 === 電子研究所 === 77 ===

Bibliographic Details
Main Authors:	WU, JI-LI, 吳基立
Other Authors:	SHEN, WEN-REN
Format:	Others
Language:	zh-TW
Published:	1989
Online Access:	http://ndltd.ncl.edu.tw/handle/14874956461527063537

Description
Summary:	碩士 === 國立交通大學 === 電子研究所 === 77 ===