A parallel pattern mixed-level fault simulator
碩士 === 國立交通大學 === 電子研究所 === 77 ===
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1989
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Online Access: | http://ndltd.ncl.edu.tw/handle/93649544133439722866 |
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ndltd-TW-077NCTU24300142016-07-29T04:13:08Z http://ndltd.ncl.edu.tw/handle/93649544133439722866 A parallel pattern mixed-level fault simulator 一個並行圖樣混合階層錯誤模擬器 HUANG, ZHI-SONG 黃志松 碩士 國立交通大學 電子研究所 77 LI, CHONG-REN SHEN, WEN-REN 李崇仁 沈文仁 1989 學位論文 ; thesis 57 zh-TW |
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NDLTD |
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zh-TW |
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Others
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description |
碩士 === 國立交通大學 === 電子研究所 === 77 ===
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author2 |
LI, CHONG-REN |
author_facet |
LI, CHONG-REN HUANG, ZHI-SONG 黃志松 |
author |
HUANG, ZHI-SONG 黃志松 |
spellingShingle |
HUANG, ZHI-SONG 黃志松 A parallel pattern mixed-level fault simulator |
author_sort |
HUANG, ZHI-SONG |
title |
A parallel pattern mixed-level fault simulator |
title_short |
A parallel pattern mixed-level fault simulator |
title_full |
A parallel pattern mixed-level fault simulator |
title_fullStr |
A parallel pattern mixed-level fault simulator |
title_full_unstemmed |
A parallel pattern mixed-level fault simulator |
title_sort |
parallel pattern mixed-level fault simulator |
publishDate |
1989 |
url |
http://ndltd.ncl.edu.tw/handle/93649544133439722866 |
work_keys_str_mv |
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