A high performance and testable CMOS PLA automatic generator for VLSI system design

A high performance and testable CMOS PLA automatic generator for VLSI system design

碩士 === 國立交通大學 === 電子研究所 === 75 ===

Bibliographic Details
Main Authors: SHI, GI-YU, 石啟宇
Other Authors: CHEN, WEN-REN
Format: Others
Language:zh-TW
Published: 1987
Online Access:http://ndltd.ncl.edu.tw/handle/01825598049974944270
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spelling ndltd-TW-075NCTU24300382016-02-12T04:10:33Z http://ndltd.ncl.edu.tw/handle/01825598049974944270 A high performance and testable CMOS PLA automatic generator for VLSI system design 為提供超大型積體電路設計而建立的高性能且可測試的互補式金氧半可程式化邏輯陣列的自動產生器 SHI, GI-YU 石啟宇 碩士 國立交通大學 電子研究所 75 CHEN, WEN-REN 沈文仁 1987 學位論文 ; thesis 0 zh-TW
collection NDLTD
language zh-TW
format Others
sources NDLTD
description 碩士 === 國立交通大學 === 電子研究所 === 75 ===
author2 CHEN, WEN-REN
author_facet CHEN, WEN-REN
SHI, GI-YU
石啟宇
author SHI, GI-YU
石啟宇
spellingShingle SHI, GI-YU
石啟宇
A high performance and testable CMOS PLA automatic generator for VLSI system design
author_sort SHI, GI-YU
title A high performance and testable CMOS PLA automatic generator for VLSI system design
title_short A high performance and testable CMOS PLA automatic generator for VLSI system design
title_full A high performance and testable CMOS PLA automatic generator for VLSI system design
title_fullStr A high performance and testable CMOS PLA automatic generator for VLSI system design
title_full_unstemmed A high performance and testable CMOS PLA automatic generator for VLSI system design
title_sort high performance and testable cmos pla automatic generator for vlsi system design
publishDate 1987
url http://ndltd.ncl.edu.tw/handle/01825598049974944270
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