A new computer-aided design of well-type guard ring in CMOS/VLSI

A new computer-aided design of well-type guard ring in CMOS/VLSI

碩士 === 國立交通大學 === 電子研究所 === 75 ===

Bibliographic Details
Main Authors:	HUANG, ZHI-YUO, 黃至堯
Other Authors:	CHEN, MING-ZHE
Format:	Others
Language:	zh-TW
Published:	1987
Online Access:	http://ndltd.ncl.edu.tw/handle/50783234044931950517

Similar Items

Characterization, simulation, and modeling of minority-carrier well-type guard rings in epitaxial CMOS
by: 黃至堯
Published: (1994)

Fabrication, characterization, and optimal design of well-type guard rings in EPI-CMOS/VLSI
by: CHEN, XIAN-ZHONG, et al.
Published: (1987)

THE DESIGN AND ANALYSIS OF NEW CMOS DIFFERENTIAL LOGIC CLRCUITS FOR VLSI APPLICATIONS
by: Hong-Yi Huang, et al.
Published: (1994)

CMOS VLSI circuits for imaging
by: Wang, Guoyu
Published: (1993)

An integrated VLSI computer-aided design system
by: XIAO, RU-XUAN, et al.
Published: (1986)

Power estimation for CMOS VLSI circuits
by: Ruey Wen Tsay, et al.
Published: (1993)

Setting CMOS environment for VLSI design
by: Chung, Chih-Ping
Published: (1989)

Design of a Low-Power VLSI Cell Library Exploiting Different Types of CMOS Logic Circuits
by: Huang, Po-Shin, et al.
Published: (1998)

The Behavior of Bilateral Latch-Up Triggering in VLSI CMOS Protection Circuits
by: Heng-Sheng Huang, et al.
Published: (1993)

Multilevel circuit partitioning for computer-aided VLSI design
by: Cheon, Yongseok
Published: (2008)

Optimization Problems in Computer-Aided-Design of VLSI circuits
by: Yu-Chung Lin, et al.
Published: (2001)

Supply current estimation in CMOS VLSI circuits
by: Rouatbi, Fredj
Published: (1992)

Timing verification in digital CMOS VLSI design
by: Yang, Hai-Gang
Published: (1991)

Modeling of substrate transger resistance in CMOS/VLSI
by: CHEN, ZHENG-XIU, et al.
Published: (1988)

Computer simulations of short-channel counter-implanted P-channel MOSFET's CMOS/VLSI
by: XIE,SHI-ZHAO, et al.
Published: (1991)

A New Statistical Method for Maximum Power Estimation in CMOS VLSI Circuits
by: N. E. Evmorfopoulos, et al.
Published: (2000-01-01)

Water is life, guard it well
by: Abd Razak, Dzulkifli
Published: (2008)

PtSi properties and applications on CMOS VLSI circuits
by: CUI, BING-YUE, et al.
Published: (1987)

Correlation-based networks for implementaion in CMOS analogue VLSI
by: Ngole, Jey E. E.
Published: (1995)

The BiCMOS dynamic digital circuits for VLSI systems
by: LIAO, HONG-REN, et al.
Published: (1992)

VLSI implementation of neural network based on subthreshold CMOS
by: ZHAO,DA-WEI, et al.
Published: (1991)

Circuit Techniques Suitable for Low-Voltage CMOS VLSI
by: Stanley Bo-Ting Wang, et al.
Published: (2000)

Modeling of Silicon-on-Insulator (SOI) CMOS VLSI Devices
by: Su Ke-Wei, et al.
Published: (1998)

Compact Modeling of SOI and Bulk CMOS VLSI Devices
by: Shih-Chia Lin, et al.
Published: (2001)

Wireless Non-Directive CMOS VLSI Infrared Transceiver
by: Wei-Chung Wang, et al.
Published: (1995)

Automated performance optimisation of combinational VLSI CMOS structures
by: Mather, Peter James
Published: (1995)

Design of analog VLSI circuits in BICMOS/CMOS technology /
by: Zarabadi, Seyed Ramezan
Published: (1992)

Low power techniques for global communication in CMOS VLSI
by: Stan, Mircea Raducu
Published: (1996)

PERFORMANCE OF LEAKAGE POWER MINIMIZATION TECHNIQUE FOR CMOS VLSI TECHNOLOGY
by: T. Tharaneeswaran, et al.
Published: (2012-06-01)

Low-power digital CMOS VLSI circuits and design methodologies
by: Khellah, Muhammad M.
Published: (2006)

Current domain analogue-to-digital conversion techniques for CMOS VLSI
by: Bracey, Mark
Published: (1997)

Low-power digital CMOS VLSI circuits and design methodologies
by: Khellah, Muhammad M.
Published: (2006)

CMOS VLSI implementation of the Quick Look Global Positioning System
by: Rothman, Daniel J
Published: (2008)

A New Solution to Analysis of CMOS Ring Oscillators
by: P. M. Farahabadi, et al.
Published: (2009-03-01)

Analysis of Radiation in LPCVD Furnace - Guard Rings and Holders
by: Chung-Ming Wang, et al.
Published: (1999)

Si Substrate Noise Coupling and Guard Ring Analysis
by: Chih-yu Yen, et al.
Published: (2010)

The Corner Effect of the High Voltage Guard Ring for IGBT
by: Lin, Shu Huey, et al.
Published: (1996)

Toeplitz matrix problems, finite rings and VLSI architectures
by: Zarowski, Christopher J.
Published: (2013)

Toeplitz matrix problems, finite rings and VLSI architectures
by: Zarowski, Christopher J.
Published: (2013)

An Adaptive Body-Bias Generator for Low Voltage CMOS VLSI Circuits
by: Ashok Srivastava, et al.
Published: (2008-01-01)

Cannot write session to /tmp/vufind_sessions/sess_o08vlncvp6708cdp12mg6uipcq