VLSI architecture for the multiplier of finite fields

VLSI architecture for the multiplier of finite fields

碩士 === 國立成功大學 === 電機工程研究所 === 75 ===

Bibliographic Details
Main Authors:	HONG, BAO-SAN, 洪寶山
Other Authors:	WANG, JUN-FA
Format:	Others
Language:	zh-TW
Published:	1987
Online Access:	http://ndltd.ncl.edu.tw/handle/57936396793607430851

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