Design of a configurable VLSI chip for gray-scale morphological operations
碩士 === 國立成功大學 === 資訊工程研究所 === 75 ===
Main Author: | 陳哲生 |
---|---|
Other Authors: | LUO, GNG-CHANG |
Format: | Others |
Language: | zh-TW |
Published: |
1992
|
Online Access: | http://ndltd.ncl.edu.tw/handle/05555799201425972751 |
Similar Items
-
Design of Highly Efficient VLSI Arichecture for Configurable DWT
by: Wen-Yi Chen, et al.
Published: (2002) -
VLSI Implementation of a Run-time Configurable Computing Integrated Circuit - The Stallion Chip
by: He, Yingchun
Published: (2014) -
VLSI Design of Back Propagation Networks with On-Chip Learning
by: Gang-Yaw Kuo, et al.
Published: (2002) -
A VLSI chip set design for the discrete Fourier transform
by: ZHONG, GI-GUN, et al.
Published: (1988) -
VLSI Design of A Polygonal Field Programmable Interconnect Chip
by: Chan Wu-Pin, et al.
Published: (1999)