Integrated entry and verification system for VLSI design

Integrated entry and verification system for VLSI design

碩士 === 國立臺灣大學 === 電機工程研究所 === 74 ===

Bibliographic Details
Main Authors:	YUAN, YUN-ZHONG, 袁允中
Other Authors:	PANG, TAI-MIN
Format:	Others
Language:	zh-TW
Published:	1986
Online Access:	http://ndltd.ncl.edu.tw/handle/91917311693474696239

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