Integrated entry and verification system for VLSI design

Integrated entry and verification system for VLSI design

碩士 === 國立臺灣大學 === 電機工程研究所 === 74 ===

Bibliographic Details
Main Authors: YUAN, YUN-ZHONG, 袁允中
Other Authors: PANG, TAI-MIN
Format: Others
Language:zh-TW
Published: 1986
Online Access:http://ndltd.ncl.edu.tw/handle/91917311693474696239
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spelling ndltd-TW-074NTU024420672016-07-22T04:08:53Z http://ndltd.ncl.edu.tw/handle/91917311693474696239 Integrated entry and verification system for VLSI design 整合式超大型積體電路輸入及驗證系統 YUAN, YUN-ZHONG 袁允中 碩士 國立臺灣大學 電機工程研究所 74 PANG, TAI-MIN FENG, WU-XIONG YU, HUI-ZHONG 龐台銘 馮武雄 丁惠中 1986 學位論文 ; thesis 0 zh-TW
collection NDLTD
language zh-TW
format Others
sources NDLTD
description 碩士 === 國立臺灣大學 === 電機工程研究所 === 74 ===
author2 PANG, TAI-MIN
author_facet PANG, TAI-MIN
YUAN, YUN-ZHONG
袁允中
author YUAN, YUN-ZHONG
袁允中
spellingShingle YUAN, YUN-ZHONG
袁允中
Integrated entry and verification system for VLSI design
author_sort YUAN, YUN-ZHONG
title Integrated entry and verification system for VLSI design
title_short Integrated entry and verification system for VLSI design
title_full Integrated entry and verification system for VLSI design
title_fullStr Integrated entry and verification system for VLSI design
title_full_unstemmed Integrated entry and verification system for VLSI design
title_sort integrated entry and verification system for vlsi design
publishDate 1986
url http://ndltd.ncl.edu.tw/handle/91917311693474696239
work_keys_str_mv AT yuanyunzhong integratedentryandverificationsystemforvlsidesign
AT yuányǔnzhōng integratedentryandverificationsystemforvlsidesign
AT yuanyunzhong zhěnghéshìchāodàxíngjītǐdiànlùshūrùjíyànzhèngxìtǒng
AT yuányǔnzhōng zhěnghéshìchāodàxíngjītǐdiànlùshūrùjíyànzhèngxìtǒng
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