Systolic array mapping of sequential algorithm for VLSI architecture

Systolic array mapping of sequential algorithm for VLSI architecture

碩士 === 國立成功大學 === 電機工程研究所 === 74 ===

Bibliographic Details
Main Authors: MA, YI-ZHENG, 馬譯政
Other Authors: WANG, JUN-FA
Format: Others
Language:zh-TW
Published: 1986
Online Access:http://ndltd.ncl.edu.tw/handle/89888402865063130518
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spelling ndltd-TW-074NCKU24420702015-10-13T12:37:08Z http://ndltd.ncl.edu.tw/handle/89888402865063130518 Systolic array mapping of sequential algorithm for VLSI architecture 轉換順序演算法成為超大型積體電路心臟壓縮型陣列之研究 MA, YI-ZHENG 馬譯政 碩士 國立成功大學 電機工程研究所 74 WANG, JUN-FA LI, ZHAO-YAN 王駿發 李肇嚴 1986 學位論文 ; thesis 0 zh-TW
collection NDLTD
language zh-TW
format Others
sources NDLTD
description 碩士 === 國立成功大學 === 電機工程研究所 === 74 ===
author2 WANG, JUN-FA
author_facet WANG, JUN-FA
MA, YI-ZHENG
馬譯政
author MA, YI-ZHENG
馬譯政
spellingShingle MA, YI-ZHENG
馬譯政
Systolic array mapping of sequential algorithm for VLSI architecture
author_sort MA, YI-ZHENG
title Systolic array mapping of sequential algorithm for VLSI architecture
title_short Systolic array mapping of sequential algorithm for VLSI architecture
title_full Systolic array mapping of sequential algorithm for VLSI architecture
title_fullStr Systolic array mapping of sequential algorithm for VLSI architecture
title_full_unstemmed Systolic array mapping of sequential algorithm for VLSI architecture
title_sort systolic array mapping of sequential algorithm for vlsi architecture
publishDate 1986
url http://ndltd.ncl.edu.tw/handle/89888402865063130518
work_keys_str_mv AT mayizheng systolicarraymappingofsequentialalgorithmforvlsiarchitecture
AT mǎyìzhèng systolicarraymappingofsequentialalgorithmforvlsiarchitecture
AT mayizheng zhuǎnhuànshùnxùyǎnsuànfǎchéngwèichāodàxíngjītǐdiànlùxīnzàngyāsuōxíngzhènlièzhīyánjiū
AT mǎyìzhèng zhuǎnhuànshùnxùyǎnsuànfǎchéngwèichāodàxíngjītǐdiànlùxīnzàngyāsuōxíngzhènlièzhīyánjiū
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