Latch-based Performance Optimization for FPGAs
We explore using pulsed latches for timing optimization -- a first in the academic FPGA community. Pulsed latches are transparent latches driven by a clock with a non-standard (i.e. not 50%) duty cycle. As latches are already present on commercial FPGAs, their use for timing optimization can avoid t...
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| Language: | en_ca |
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2012
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| Online Access: | http://hdl.handle.net/1807/32631 |