| Summary: | The objective of this work was to integrate an optical receiver in a modern standard
technology in a form amenable to multiple lanes. To accomplish this goal, a photodiode
was integrated with the receiver in a standard 90nm CMOS process and the nominal
process voltage of 1.2V was not exceeded. Two optical lanes were integrated on chip
with a pitch compatible with existing industry photodiode arrays. This work uses
a non-SML photodiode to increase optical responsivity to 0.141A/W, almost 3 times
higher than values typically reported for SML photodiodes. This receiver is the first
integrated optical receiver reported in a standard CMOS technology with a feature
size smaller than 0.13μm, which is necessary for the eventual integration of optical
receivers with modern digital processing blocks on a single die. The traditional analog
equalizer used in most integrated optical receivers is replaced with a high-pass filter and
hysteresis latch for equalization. The receiver occupies a core area of 0.197mm2 and
has an optical sensitivity of -3.7dBm at a 2Gbps data rate, while consuming 46.3mW.
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